SIMD Acceleration for HEVC Decoding

Saliency-Guided Complexity Control for HEVC Decoding

The latest High Efficiency Video Coding (HEVC) standard significantly improves coding efficiency over its previous video coding standards. The expense of such improvement is enormous computational complexity, from both encoding and decoding sides. Since computational capability and power capacity are diverse across portable devices, it is necessary to reduce decoding complexity to a target with...

An Efficient Interpolation Hardware Architecture for HEVC Inter-Prediction Decoding

This paper proposes an efficient hardware architecture for high efficiency video coding (HEVC), which is the next generation video compression standard. It adopts several new coding techniques to reduce the bit rate by about 50% compared with the previous one. Unlike the previous H.264/AVC 6-tap interpolation filter, in HEVC, a one-dimensional seven-tap and eight-tap filter is adopted for luma ...

Implementation of fast HEVC encoder based on SIMD and data-level parallelism

This paper presents several optimization algorithms for a High Efficiency Video Coding (HEVC) encoder based on single instruction multiple data (SIMD) operations and data-level parallelism. Based on the analysis of the computational complexity of HEVC encoder, we found that interpolation filter, cost function, and transform take around 68% of the total computation, on average. In this paper, se...

Time Optimization of HEVC Encoder over X 86 Processors using SIMD Spring 2013 Multimedia Processing

GPU Acceleration for Particle Filter based LDPC Decoding

A parallel belief propagation algorithm based on Particle Filtering (PF) for channel estimation and Low-Density Parity-Check (LDPC) decoding is presented in this paper based on Compute Unified Device Architecture (CUDA). The authors have found that compared with the traditional Belief Propagation (BP) algorithm with fixed estimated noise power, BP algorithm based on PF [1] not only gives a good...